Random access memory (RAM) is a type of storage for computing devices. RAM is typically associated with volatile memory that is implemented in integrated circuits and in which stored information is lost when power provided to the RAM is switched off.
One type of RAM is known as double-data-rate synchronous dynamic random access memory (DDR SDRAM). DDR SDRAM is typically used in computing applications that require high bandwidth and low latency memory access. One version of this memory technology is known as DDR3 SDRAM, which can provide for high performance data rates, high bandwidth, high density, and low power consumption relative to earlier generations of SDRAM.
The high bandwidth and high operating frequencies required to drive DDR SDRAM can be problematic as they can make the controller to memory interface electrically complex due to signal integrity considerations. A DDR3 SDRAM controller (herein, “controller”) needs to transmit signals to associated DDR3 SDRAM memory (herein, “memory”) for the operation of the memory on a printed circuit board (“PCB”) (herein, “board”). The memory includes multiple pins. Each one of the pins of the memory receives a specific type of information (e.g., a bit of an address, reset instruction, etc). The controller is physically designed to include pads that individually correspond to one of the pins. Herein, any reference to pin(s) or pad(s) may refer to a same type of physical components. Each one of the pads may transmit a signal for a specific type of information to a corresponding pin of the memory. In other words, each pin of a memory is driven by an equivalent pad of a controller.
A controller may be used for different types of memory that have different configuration of pins. Often, different controllers need to be used for different instances of a same type of memory based on where each one of the instances is placed on a board (i.e., board layout). For the physical design of the controller to be reused, physical connections need to be fixed between pins of the memory and corresponding pads of the controller. As a result, crossovers occur and additional layers may need to be added to the board to accommodate tight skew requirements of the high bandwidth, further increasing routing complexity on the board and signal routing congestion. The problems associated with reusing a particular controller for different types of memory, or for different instances of a same type of memory with different board layouts, make the practice, currently, practically impossible.
A physical design of a controller may be tailored for each type of board (e.g., each memory device). A controller tailored for a particular physical design of memory may not be used with memory devices that have different configurations of pins. In other words, a controller with a particular physical design may only be used for a particular type of memory. Accordingly, a single controller cannot be used with multiple devices that have different physical configurations. This solution is inefficient, non-scalable, and requires a fixed layout for every board using a particular controller. Forcing boards to have the same type of layout for the boards to interact with a particular controller impedes placement of memory and routing optimization.